Power in a CMOS (complimentary metal oxide semiconductor) circuit can be characterized by:P=c×v2×f  (1)where P=power, c=switching capacitance, v=supply voltage, and f=switching frequency. Since power consumption is a criteria evaluated in designing conventional circuits, and since changing the supply voltage yields a quadratic effect on power consumption, supply voltage is frequently manipulated in circuits in an attempt to conserve power. For example, supply voltage may be reduced when a processor enters a “sleep” or “standby” mode. However, switching frequency in CMOS is typically directly proportional to supply voltage. Thus, the switching frequency changes as the supply voltage changes. For example, as the supply voltage decreases the switching frequency should also decrease.
To achieve an average chip frequency higher than the frequency associated with the minimum voltage across a chip over time, it is necessary to quickly adapt (e.g., reduce) cycle time in response to a voltage drop created when the supply voltage is manipulated (e.g., when chip goes into a power saving mode). Traditional clock generators like phase locked loops (PLL) and delay locked loops (DLL) do not satisfactorily adapt the cycle time due, for example, to locking time delays. In one example, when the output frequency of a typical PLL changes, there is a relatively long (e.g., milliseconds) wait for the PLL to get locked. Additionally, due to process, voltage, and temperature variations, the PLL lock time may be unpredictable. In another example, an open loop voltage controlled oscillator (VCO) running off a chip supply may rapidly adapt its frequency to voltage changes. However, its frequency is unpredictable from part to part, even for substantially identical chip behavior.